Electronic circuit design discusions :: power consumption of integrated circuit in 0.13m CMOS technology


	power consumption of integrated circuit in 0.13m CMOS technology Hi all, currently I am investigating a data sorting algorithm on hardware. The algorithm was implemented in VHDL and is currently running on a Xilinx Virtex-II Pro XC2VP70 - FF1704 FPGA. Power consumption is a crucial aspect in the target application. Therefore I made an analysis with the Xilinx Virtex-II Pro Web Power Tool (www.xilinx.com) and obtained satisfying results. Now I'd like to make an estimation what this circuit would consume on a comparable ASIC 0.13m CMOS technology (the FPGA is also based on a 0.13m CMOS technology). The target clock frequency is 180 MHz, activity ratio is 15%. Is there any rule of thumb or calculation rule? Any help is highly appreciated !!!! Regards Gero - Hide quoted text - Geronimo Stempovski wrote: > Hi all, > currently I am investigating a data sorting algorithm on hardware. The > algorithm was implemented in VHDL and is currently running on a Xilinx > Virtex-II Pro XC2VP70 - FF1704 FPGA. Power consumption is a crucial aspect > in the target application. Therefore I made an analysis with the Xilinx > Virtex-II Pro Web Power Tool (www.xilinx.com) and obtained satisfying > results. > Now I'd like to make an estimation what this circuit would consume on a > comparable ASIC 0.13m CMOS technology (the FPGA is also based on a 0.13m > CMOS technology). The target clock frequency is 180 MHz, activity ratio is > 15%. Is there any rule of thumb or calculation rule? > Any help is highly appreciated !!!! > Regards Gero power is .5cv*2fsf. Sounds like you know everything but C. So you would need to synthesize or otherwise get a gate count, assume a load per gate and go from there. -- Del Cecchi "This post is my own and doesnt necessarily represent IBMs positions, strategies or opinions. -----------------------------------------------Reply----------------------------------------------- C F * V^2 = P There is no "1/2", as you get power when you charge, and also when you discharge a node. E=1/2 CFV^2 is appropriate for energy stored in a capacitor, not for the power dissipated when nodes are switching (Charging AND Dis-charging). Austin -----------------------------------------------Reply----------------------------------------------- austin wrote: > C * F * V^2 = P > There is no "1/2", as you get power when you charge, and also when you > discharge a node. > E=1/2 CFV^2 is appropriate for energy stored in a capacitor, not for the > power dissipated when nodes are switching (Charging AND Dis-charging). > Austin true for clocks but data lines usually only transition one direction per cycle at most. so conventionally SF=2 for clocks in power calculators. -- Del Cecchi "This post is my own and doesnt necessarily represent IBMs positions, strategies or opinions. -----------------------------------------------Reply----------------------------------------------- On Fri, 11 May 2007 14:30:20 +0200, "Geronimo Stempovski" - Hide quoted text - <geronimo.stempov@arcor.de> wrote: >Hi all, >currently I am investigating a data sorting algorithm on hardware. The >algorithm was implemented in VHDL and is currently running on a Xilinx >Virtex-II Pro XC2VP70 - FF1704 FPGA. Power consumption is a crucial aspect >in the target application. Therefore I made an analysis with the Xilinx >Virtex-II Pro Web Power Tool (www.xilinx.com) and obtained satisfying >results. >Now I'd like to make an estimation what this circuit would consume on a >comparable ASIC 0.13m CMOS technology (the FPGA is also based on a 0.13m >CMOS technology). The target clock frequency is 180 MHz, activity ratio is >15%. Is there any rule of thumb or calculation rule? >Any help is highly appreciated !!!! >Regards Gero There are several design houses that specialize in flipping fpga designs to asics. I bet one of them would give you a quick estimate. Google "fpga asic conversion service" or something like that. John -----------------------------------------------Reply----------------------------------------------- If you want to retain the 1/2, then I suggest you use T (for transition) instead of F (for frequency), in order to avoid the ambiguity. A factor of 2 might actually mean something :-) Peter Alfke On May 11, 1:43 pm, Del Cecchi <cecchinos@us.ibm.com> wrote: - Hide quoted text - > austin wrote: > > C * F * V^2 = P > > There is no "1/2", as you get power when you charge, and also when you > > discharge a node. > > E=1/2 CFV^2 is appropriate for energy stored in a capacitor, not for the > > power dissipated when nodes are switching (Charging AND Dis-charging). > > Austin > true for clocks but data lines usually only transition one direction per > cycle at most. so conventionally SF=2 for clocks in power calculators. > -- > Del Cecchi > "This post is my own and doesn't necessarily represent IBM's positions, > strategies or opinions."

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Electronic circuit design discusions

power consumption of integrated circuit in 0.13m CMOS technology